Intel leans hard on advanced chip packaging technologies in battle for computing supremacy

This text is a part of the Generation Perception sequence, made imaginable with investment from Intel.

We have a tendency to concentrate on the most recent and biggest generation nodes as a result of they’re used to fabricate the densest, quickest, maximum power-efficient processors. However as we have been reminded all through Intel’s contemporary Structure Day 2020, a spread of transistor designs is had to construct heterogeneous techniques.

“No unmarried transistor is perfect throughout all design issues,” mentioned leader architect Raja Koduri. “The transistor we want for a functionality desktop CPU, to hit super-high frequencies, may be very other from the transistor we want for high-performance built-in GPUs.”

Right here’s the issue: amassing processing cores, fixed-function accelerators, graphics sources, and I/O, after which etching all of them onto a monolithic die at 10nm makes production very, very, tough. However the choice—breaking them aside and linking the items—items demanding situations of its personal. Inventions in packaging triumph over those hurdles by means of bettering the interface between dense circuits and the forums they populate.

Advanced packaging is all about mixing and matching the right transistors for each application to speed time to market while maximizing performance.

Above: Complex packaging is all about mix and matching the proper transistors for every utility to hurry time to marketplace whilst maximizing functionality.

Again in 2018, Intel laid out a plan to get smaller units operating in combination with out sacrificing velocity. “We mentioned that we wish to broaden generation to attach chips and chiplets in a kit that may fit the functionality, chronic potency, and price of a monolithic SoC,” persevered Koduri. “We additionally mentioned we want a high-density interconnect roadmap that permits excessive bandwidth at low chronic.”

In an business keen to call winners and losers in response to procedure generation, cutting edge approaches to packaging will probably be pressure multipliers within the fight for computing supremacy. Let’s take a look at Intel’s present packaging playbook, along side the teasers disclosed all through its contemporary Structure Day 2020.


  • The Embedded Multi-die Interconnect Bridge (EMIB) facilitates die-to-die connections the usage of tiny silicon bridges embedded within the kit substrate
  • The Complex Interface Bus (AIB) is an open-source interconnect same old for developing high-bandwidth/low-power connections between chiplets
  • Foveros takes packaging to the 3rd size with stacked dies. The primary Foveros-based product will goal the gap between laptops and smartphones.
  • Co-EMIB and the Omni-Directional Interface promise scaling past Intel’s current packaging applied sciences by means of facilitating higher flexibility.

Overcoming monolithic rising pains with EMIB

Till not too long ago, in the event you sought after to get heterogeneous dies onto a unmarried kit for max functionality, you positioned the ones dies on a work of silicon known as an interposer and ran wires in the course of the interposer for conversation. Thru silicon vias (TSVs) — electric connections — handed in the course of the interposer and right into a substrate, which shaped the kit’s base.

The business refers to this as 2.5D packaging. TSMC used it to fabricate NVIDIA’s Tesla P100 accelerator again in 2016. A 12 months prior to that, AMD blended an enormous GPU and 4GB of high-bandwidth reminiscence (HBM) on a silicon interposer to create the Radeon R9 Fury X. Obviously, the generation works. Nevertheless it provides an inherent layer of complexity, chopping into yields and including important price.

Intel’s Embedded Multi-die Interconnect Bridge (EMIB) goals to mitigate the constraints of two.5D packaging by means of ditching the interposer in prefer of tiny silicon bridges embedded within the substrate layer. The bridges are loaded with micro-bumps that facilitate die-to-die connections.

“The present era of EMIB provides a 55 micron micro-bump pitch with a roadmap to get to 36 microns,” mentioned Ramune Nagisetty, director of procedure and product integration at Intel. Evaluate that to the 100-micron bump pitch of a normal natural kit. EMIB makes it imaginable to reach a lot upper bump density consequently.

Small silicon bridges also are so much more cost effective than interposers. While the Tesla P100 and Radeon R9 Fury X have been high-dollar flagships, one among Intel’s first merchandise with embedded bridges used to be Kaby Lake G, a cell platform that blended eighth-gen Core CPUs and AMD Radeon RX Vega M graphics. Laptops in response to Kaby Lake G weren’t reasonable by means of any measure. However they demonstrated EMIB’s skill to get heterogeneous dies onto one kit, consolidating treasured board area, augmenting functionality, and using down price in comparison to discrete elements.

In this example, EMIB creates a high-density connection between the Stratix 10 FPGA and two transceiver dies.

Above: On this instance, EMIB creates a high-density connection between the Stratix 10 FPGA and two transceiver dies.

Intel’s Stratix 10 FPGAs additionally make use of EMIB to attach I/O chiplets and HBM from 3 other foundries, manufactured the usage of six other generation nodes, on one kit. Through decoupling transceivers, I/O, and reminiscence from the core cloth, Intel can select and select the transistor design for every die. Including improve for CXL, sooner transceivers, or Ethernet is as simple as swapping out the ones modular tiles attached by means of EMIB.

Standardizing die to die integration with the Complex Interface Bus

Earlier than chiplets may also be blended and coupled, the reusable IP blocks will have to know the way to speak to one another over a standardized interface. For its Stratix 10 FPGAs, Intel’s embedded bridges lift the Complex Interface Bus (AIB) between its core cloth and every tile.

AIB used to be designed to permit modular integration on a kit in a lot the similar method PCI Categorical facilitates integration on a motherboard. However while PCIe drives very excessive speeds thru few wires, AIB exploits the density of EMIB to create a large parallel interface that operates at decrease clock charges, simplifying the circuitry to transmit and obtain whilst nonetheless reaching very low latency.

Reusable IP blocks on a package may be connected by silicon bridges or interposers using the Advanced Interface Bus to move data over a wide parallel connection.

Above: Reusable IP blocks on a kit is also attached by means of silicon bridges or interposers the usage of the Complex Interface Bus to transport knowledge over a large parallel connection.

The primary era of AIB provides 2 Gb/s twine signaling, enabling Intel’s imaginative and prescient of heterogeneous integration with monolithic SoC-like functionality. A second-generation model, anticipated to tape out in 2021, helps as much as 6.four Gb/s in step with twine, bump pitches as tight as 36 microns, decrease chronic in step with bit transferred, and backward compatibility with current AIB implementations.

It’s price noting that AIB is packaging agnostic. Despite the fact that Intel connects its tiles the usage of EMIB, TSMC’s Chip-on-Wafer-on-Substrate (CoWoS) generation may lift AIB, too.

Previous this 12 months, Intel turned into a member of the Commonplace Hardware for Interfaces, Processors, and Methods (CHIPS) Alliance, hosted by means of the Linux Basis, to give a contribution the AIB license as an open-source same old. The speculation, in fact, used to be to inspire business adoption and facilitate a library of AIB-equipped chiplets.

“We recently have 10 AIB-based tiles from a couple of distributors which might be both in-production or on power-on,” says Intel’s Nagisetty. “There are 10 extra tiles within the near-term horizon from ecosystem companions together with startups and college analysis teams.”

Foveros will increase density in a 3rd size

Breaking SoCs into reusable IP blocks and integrating them horizontally with high-density bridges is among the tactics Intel plans to leverage production efficiencies and proceed scaling functionality. The next move up, in step with the corporate’s packaging generation roadmap, comes to stacking dies on most sensible of one another, face-to-face, the usage of fine-pitched micro-bumps. This 3-dimensional way, which Intel calls Foveros, closes the space between dies, the usage of much less chronic to transport knowledge round. While Intel’s EMIB generation is rated at more or less zero.50 pJ/bit, Foveros will get that all the way down to zero.15 pJ/bit.

Lakefield, the first product based on Foveros 3D die stacking, comprises a base die (22FFL) under a compute die (10nm), all of which is topped by package-on-package memory.

Above: Lakefield, the primary product in response to Foveros 3-D die stacking, accommodates a base die (22FFL) underneath a compute die (10nm), all of which is crowned by means of package-on-package reminiscence.

Like EMIB, Foveros permits Intel to select the most efficient procedure generation for every layer of its stack. The primary implementation of Foveros, code-named Lakefield, crams processing cores, reminiscence keep watch over, and graphics right into a die manufactured at 10nm. That chiplet sits on most sensible of the bottom die, which contains the purposes you’d normally to find in a platform controller hub (audio, garage, PCIe, and many others.), manufactured on a 14nm low-power procedure. Micro-bumps between the 2 pipe in chronic and communications thru TSVs within the base die. Intel then tops the stack with LPDDR4X reminiscence from one among its companions.

A whole Lakefield kit measures simply 12x12x1mm, enabling a brand new magnificence of units between laptops and smartphones. However we don’t be expecting Foveros to just serve low-power programs. In a 2019 HotChips Q&A consultation, Intel fellow Wilfred Gomes predicted the generation’s long run ubiquity. “…the best way we designed Foveros, we predict it’ll span all of the vary of the computing spectrum, from the lowest-end units to the highest-end units,” he mentioned.

Scalability offers us any other variable to imagine

The packaging roadmap set forth all through Intel’s Structure Day 2020 plotted every generation by means of interconnect density (the choice of microbumps in step with sq. millimeter) and tool potency (pJ of power expended in step with bit of information transferred). Past Foveros, Intel is pursing die-on-wafer hybrid bonding to push each metrics even additional. It expects to reach greater than 10,000 bumps/mm² and no more than zero.05 pJ/bit.

Blending 2.5D and 3D packaging technologies yields Co-EMIB, which enables larger-than-reticle sized base dies plus Foveros die stacks on the same package.

Above: Mixing 2.5D and 3-D packaging applied sciences yields Co-EMIB, which allows larger-than-reticle sized base dies plus Foveros die stacks at the similar kit.

However complex packaging applied sciences can be offering application past upper bandwidth and decrease chronic. A mixture of EMIB and Foveros — dubbed Co-EMIB — guarantees scaling alternatives past both way by itself. There are not any real-world examples of Co-EMIB but. On the other hand, you’ll be able to believe huge natural applications with embedded bridges connecting Fovoros stacks that mix accelerators and reminiscence for high-performance computing.

Intel’s Omni-Directional Interface (ODI) provides much more flexibility by means of linking chiplets subsequent to one another, connecting chiplets stacked vertically, and offering chronic to the highest die in a stack at once thru copper pillars. The ones pillars are greater than the TSVs that run in the course of the base die in a Foveros stack, minimizing resistance and bettering chronic supply. The liberty to attach dies in any path and stack greater tiles on most sensible of smaller ones offers Intel much-needed flexibility in structure. It for sure looks as if a promising generation for development on Foveros’ features.

Leave a Reply

Your email address will not be published. Required fields are marked *